Field of the Invention
The invention lies in the semiconductor technology field. More specifically, the invention relates to a semiconductor memory having at least one non-volatile, dual-transistor memory cell which has the following features:
an N-channel selection transistor and an N-channel memory transistor; PA1 the N-channel selection transistor has a selection gate and two selection channels, the selection gate being connected to a row line leading to the memory cell; PA1 the N-channel memory transistor has a memory gate or a control gate and two memory channels; PA1 a second memory channel and a first selection channel are connected to one another, the other memory channel or respectively the other selection channel being connected to a column line leading to the memory cell; PA1 an N-channel selection transistor having a selection gate connected to the row line, a first selection channel connection connected to the column line and a second selection channel connection; PA1 an N-channel memory transistor having a memory gate, a first memory channel connection connected to the second selection channel connection, and a second memory channel connection; PA1 within the rows, the selection gates of a plurality of the memory cells are connected in parallel, and the memory gates of a plurality of memory cells are connected in parallel; and PA1 within the columns, the first memory channels and respectively the second selection channels are connected in parallel.
whereby the semiconductor memory has at least one transfer transistor with a first and a second transfer channel, and the first transfer channel is connected to the memory gate.
In the generic semiconductor memories, the individual transistors are implemented in FET technology on a semiconductor substrate. The memory transistor thereby has a floating gate, with the result that it can be programmed, by the application of suitable voltages to the channels and to the gate, in such a way that it can assume a desired state permanently or in a non-volatile fashion.
In order to read the memory cell, a memory channel and a selection channel are connected to one another, the other free memory channel or respectively the other free selection channel being connected to a column line leading to the memory cell. In this case, the selection transistor is driven in such a way that it turns on. If a current then flows in the event of a voltage being applied to the corresponding column line, then the memory transistor has been programmed to "conducting", or written to, in a previous step. If no current flows in the event of the voltage being applied to the column line with the selection transistor turned on, then the memory transistor has been programmed to "nonconducting", or erased, in a previous step.
EP 0317 443 A1 discloses a two-transistor memory cell comprising a selection transistor and a floating gate transistor. A special voltage is applied to the gate of the floating gate transistor for driving purposes.
In the case of the memories of the generic type, the fact that the voltages required for programming have to be generated with high technological complexity is particularly problematic. Furthermore, in the course of programming one memory cell, faults are frequently produced in other memory cells which are not currently selected for programming.